SoC MMU

FLASH and PSRAM in ESP32* chips are attached through MMU which allows mapping different parts of FLASH and/or PSRAM into fixed address ranges. It's not very well documented for the ESP32 and I can't find any documentation for ESP32S3, so here's the bits scraped from docs, IDF source code, Espressif QEMU models and good old poking into registers-checking the effect.

ESP32

ESP32S3

512 32-bit entries starting at DR_REG_MMU_TABLE (0x600C5000). First 0x180 entries control mapping of the virtual address range 0x42000000..0x43800000 connected to an IRAM bus. Next 0x80 entries control mapping of the virtual address range 0x3d800000..0x3e000000 connected to the DRAM bus. Bit 15 of the entry chooses PSRAM (if set) or FLASH (if clear), bit 14 of the entry indicates invalid entry (if set), lower bits choose one 64KByte page. There must be more entries to fill two 32MByte ranges advertised in the TRM and there may be registers that choose what ranges of MMU table correspond to what virtual addresses, unknown ATM.