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--- etc:users:jcmvbkbc:mpc85xx-qemu-linux [2010/01/18 03:12] – jcmvbkbc
+++ etc:users:jcmvbkbc:mpc85xx-qemu-linux [2016/08/08 20:53] (current) – ↷ Page moved from users:jcmvbkbc:mpc85xx-qemu-linux to etc:users:jcmvbkbc:mpc85xx-qemu-linux kel
@@ Line 52: / Line 52: @@
   * configure qemu: ../qemu/configure --enable-system --disable-linux-user --enable-fdt --target-list=ppc-softmmu --prefix=`pwd`/root "$@"
   * apply some patches :TODO:
@@ Line 63: / Line 65: @@
   * what's the initial MMU setup on entry to kernel? see arch/powerpc/kvm/e500_tlb.c, esp. kvmppc_e500_tlb_setup;
   * why exception in the first mfmsr? mmu_idx, mem_idx -- ??
-  * implement tlbsx (done), tlbre, tlbwe, tlbivax for BookE (needed by arch/powerpc/kernel/head_fsl_booke.S)
+  * implement tlbsx (done), tlbre (done), tlbwe (done), tlbivax (done) for BookE (needed by arch/powerpc/kernel/head_fsl_booke.S)
   * how softmmu works? how to substitute existing PPC softmmu by TLB-based one?
+  * what is hardware TLB entry replacement policy/hash function?
+  * need to refactor the whole TLB thing for BookE PPC
 ===== References =====
-PowerISA 2.06: http://www.power.org/resources/downloads/PowerISA_V2.06_PUBLIC.pdf
+  * [[http://www.power.org/resources/downloads/PowerISA_V2.06_PUBLIC.pdf|PowerISA 2.06]]
+  * [[http://www.google.ru/url?sa=t&source=web&ct=res&cd=3&ved=0CBMQFjAC&url=http%3A%2F%2Fwww.freescale.com%2Ffiles%2F32bit%2Fdoc%2Fref_manual%2FE500CORERM.pdf&rct=j&q=e500corerm.pdf&ei=BbNbS7WpOsyF-AaL1tD4CQ&usg=AFQjCNHTUfqYcCfN1rAgkHpbeyJnSCF-WQ|E500 core reference manual (e500corerm.pdf)]]