etc:users:jcmvbkbc:qemu-target-xtensa
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etc:users:jcmvbkbc:qemu-target-xtensa [2011/04/21 15:01] – progress jcmvbkbc | etc:users:jcmvbkbc:qemu-target-xtensa [2024/01/21 19:22] (current) – jcmvbkbc | ||
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====== QEMU support for Xtensa ====== | ====== QEMU support for Xtensa ====== | ||
- | Git tree: http://jcmvbkbc.spb.ru/git/?p=dumb/qemu-xtensa.git;a=shortlog;h=refs/heads/xtensa | + | * Git tree: https:// |
+ | * Official QEMU wiki feature page: [[http://wiki.qemu.org/Features/Xtensa]] | ||
+ | * Official xtensa linux wiki page: [[https://wiki.linux-xtensa.org/ | ||
+ | |||
+ | ===== Description ===== | ||
+ | qemu/target-xtensa is a project aimed at development of a free simulator for Tensilica Xtensa processor family. | ||
+ | |||
+ | Although xtensa instruction set specification is open and there' | ||
+ | |||
+ | The project was initiated to lower cost and to speed up development of one of the Motorola Solutions projects and has been carried out exclusively by the [[http:// | ||
+ | |||
+ | Our goal is to make it usable (and preferable: | ||
+ | |||
+ | ===== Now active ===== | ||
+ | * TIE support | ||
+ | |||
+ | ===== TODO ===== | ||
+ | * xtensa | ||
+ | |||
+ | ===== Implementation status ===== | ||
- | ===== Things to do ===== | ||
* core/basic opcodes implementation; | * core/basic opcodes implementation; | ||
* [+] and/ | * [+] and/ | ||
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* [+] call0, callx0, j, b*; | * [+] call0, callx0, j, b*; | ||
* [+] l32*, s32*; | * [+] l32*, s32*; | ||
- | * [-] accurate SR write semantics; | + | * [+] accurate SR write semantics; |
- | * [-] boolean registers/ | + | * options |
- | * windowed registers; | + | * [+] windowed registers; |
- | * [+] call*/ | + | * [+] call*/ |
- | * [+] simple overflow algorithm that's triggered from ENTER; | + | * [+] accurate overflow triggering; |
- | * [-] accurate overflow triggering; | + | * [+] loop option; |
- | * [+] loop option; | + | * [+] extended L32R option; |
- | * [+] extended L32R option; | + | * [+] MAC16; |
- | * [-] floating point; | + | * [+] coprocessors; |
- | * MMU; | + | * [+] floating point; |
- | * [+] no-mmu mode; | + | * [+] boolean registers/ |
- | * [-] region protection (with/ | + | |
+ | | ||
+ | * [+] region protection (with/ | ||
+ | * [+] MMU; | ||
+ | * [+] MPU; | ||
+ | * cache options; | ||
+ | * [+] memory attributes; | ||
+ | * [+] memory accessibility check; | ||
+ | * [-] memory access timing; | ||
+ | * [+] debug option; | ||
+ | * exceptions; | ||
+ | * [+] debug (only external); | ||
+ | * [+] break; | ||
+ | * [+] window overflow/ | ||
+ | * [+] user/kernel (invalid insn, privileged insn, alignment, division by 0,...); | ||
+ | * [+] relocatable vectors; | ||
+ | * [+] external interrupts; | ||
+ | * [+] timer interrupts; | ||
+ | * [+] qemu timer to avoid busy looping in waiti; | ||
+ | * [+] FLIX; | ||
+ | * [+] wide branches; | ||
* gdbserver; | * gdbserver; | ||
- | * [+] xml register map, read/write register; | + | * [+] read/write register, < |
- | * [-] correct SR mapping; | + | * [+] correct SR mapping; |
* [+] debug exception, single step mode; | * [+] debug exception, single step mode; | ||
* [+] hw/sw breakpoints; | * [+] hw/sw breakpoints; | ||
- | | + | |
- | * [+] debug (only external); | + | * evaluation board; |
- | * [+] window overflow/ | + | * [+] sim platform; |
- | * [+] user/kernel | + | * xt2000 platform; |
- | * [-] relocatable vectors; | + | * [+] UART (reuse existing 16550 serial); |
- | * [-] external | + | * [+] xtsonic (reuse existing dp8393x NIC); |
- | * sample evaluation board; | + | * [-] LED; |
- | * [+] memory mapping, ELF loader; | + | * [+] lx200/60/110 platform; |
- | * [-] standard peripherals; | + | * [+] UART (reuse existing 16550 serial); |
- | * [-] external configuration (a-la xtensa | + | * [+] opencores ethernet; |
- | * [-] automatic regression test suite; | + | * [+] [[.:qemu-target-xtensa: |
+ | * [+] PCI controller | ||
+ | * [-] hardcoded IRQ routing may connect legacy PCI IRQ to edge-triggered | ||
+ | * [+] [[.: | ||
+ | * simulation quality; | ||
+ | * [+] pass command line arguments to argc/argv SIMCALLs; | ||
+ | * [+] TB chaining; | ||
+ | * [+] external configuration (overlay | ||
+ | * [+] [[.: | ||
+ | * [+] SMP support (interrupt distributor, | ||
+ | * [-] [[.: | ||
===== Events ===== | ===== Events ===== | ||
* 2011.04.20: C++ 'hello world' is working in qemu (stdio, stdlib, simcalls, windowed registers, loops, ext l32r) (: | * 2011.04.20: C++ 'hello world' is working in qemu (stdio, stdlib, simcalls, windowed registers, loops, ext l32r) (: | ||
+ | * 2011.04.26: multithreaded ThreadX application is working in qemu (timer interrupts) | ||
+ | * 2011.04.30: preparation for qemu mainline submission started | ||
+ | * 2011.05.04: first RFC patchset sent to qemu-devel http:// | ||
+ | * 2011.05.18: first PATCH patchset sent to qemu-devel http:// | ||
+ | * 2011.06.19: [[xtensa-linux|linux boots]], issues on userspace application startup | ||
+ | * 2011.06.22: successfull userspace app startup in linux | ||
+ | * 2011.06.29: xtensa linux session on qemu-xtensa was available at ssh -p 3333 xtensa@jcmvbkbc.spb.ru | ||
+ | * 2011.07.18: issue with gdb not able to read privileged SRs root-caused: | ||
+ | * 2011.07.19: tensilica guys suggested the following solution for gdb: | ||
+ | < | ||
+ | I guess you can just make sure you don't mark new registers as PRIVILEGED in | ||
+ | | ||
+ | </ | ||
+ | * 2011.07.24: second PATCH patchset sent to qemu-devel http:// | ||
+ | * 2011.09.01: third PATCH patchset sent to qemu-devel http:// | ||
+ | * 2011.09.02: fourth PATCH patchset sent to qemu-devel http:// | ||
+ | * 2011.09.06: fifth PATCH patchset sent to qemu-devel http:// | ||
+ | * 2011.09.10: fifth PATCH patchset hit the qemu mainline: http:// | ||
+ | * 2011.09.27: linux booted up to rootfs mounting on the new emulated LX200 board | ||
+ | * 2011.10.01: complete linux bootup via NFS on the LX200 | ||
+ | * 2011.10.10: lx60, opencores ethernet, overlay reuse and MAC16 patches sent to qemu-devel | ||
+ | * 2011.10.16: lx60, opencores ethernet, overlay reuse and MAC16 patches are merged | ||
+ | * 2011.10.29: lx60/lx200: u-boot starts from FLASH, linux kernel boots via TFTP | ||
+ | * 2011.11.03: emulation speed test for sha512sum running in linux on dc232b shows fantastic 266 MIPS | ||
+ | * 2011.11.22: linux for dc233c is working on qemu | ||
+ | * 2012.01.13: instruction breakpoints are working | ||
+ | * 2012.01.29: data breakpoints are working | ||
+ | * 2012.03.03: debug option is merged | ||
+ | * 2012.09.09: FP coprocessor series is posted to qemu-devel | ||
+ | * 2012.09.19: FP coprocessor series is in the mainline | ||
+ | * 2014.06.29: uImage/ | ||
+ | * 2017.01.25: CCOUNT no longer counts instructions; | ||
+ | * 2018.01.09: libisa and target disassembler series is in the mainline | ||
+ | * 2018.01.24: xtensa noMMU series is in the mainline | ||
+ | * 2018.03.17: xtensa linux-user series is in the mainline | ||
+ | * 2019.01.30: basic FLIX 'hello world' is working | ||
+ | * 2019.02.05: xtensa SMP support series is in the mainline | ||
+ | * 2019.03.01: xtensa FLIX support series is in the mainline | ||
+ | * 2019.09.12: xtensa call0 ABI is supported by linux-user in the mainline | ||
+ | * 2019.10.24: xtensa [[.: | ||
+ | * 2020.08.24: xtensa DFPU support series is in the mainline | ||
+ | * 2021.03.10: it's been 10 years | ||
+ | * 2024.01.13: control/ |
etc/users/jcmvbkbc/qemu-target-xtensa.1303383713.txt.gz · Last modified: 2011/04/21 15:01 by jcmvbkbc