http://wiki.osll.ru/ Sat, 30 May 2026 03:15:45 +0000 FeedCreator 1.8 http://wiki.osll.ru/lib/tpl/dokuwiki/images/favicon.ico http://wiki.osll.ru/ http://wiki.osll.ru/doku.php/etc:users:jcmvbkbc:linux-xtensa:esp32s3:gpio?rev=1707122044&do=diff GPIO and pin muxing Take a look at the esp32s3 TRM chapter 6.3, table 6.2 and table 6.3 to understand relation between the peripheral signals, IO MUX and the GPIO matrix. Teaser picture: IO MUX pin settings (selected function, drive strength, pull-up, pull-down, input enable) are controlled by the children of the anonymous@undisclosed.example.com (Anonymous) etc:users:jcmvbkbc:linux-xtensa:esp32s3 Mon, 05 Feb 2024 11:34:04 +0000 http://wiki.osll.ru/doku.php/etc:users:jcmvbkbc:linux-xtensa:esp32s3:mmu?rev=1707431734&do=diff SoC MMU FLASH and PSRAM in ESP32* chips are attached through MMU which allows mapping different parts of FLASH and/or PSRAM into fixed address ranges. It's not very well documented for the ESP32 and I can't find any documentation for ESP32S3, so here's the bits scraped from docs, IDF source code, Espressif QEMU models and good old poking into registers-checking the effect. anonymous@undisclosed.example.com (Anonymous) etc:users:jcmvbkbc:linux-xtensa:esp32s3 Fri, 09 Feb 2024 01:35:34 +0000