etc:users:jcmvbkbc:linux-xtensa:esp32s3:gpio
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etc:users:jcmvbkbc:linux-xtensa:esp32s3:gpio [2024/02/02 17:33] – created jcmvbkbc | etc:users:jcmvbkbc:linux-xtensa:esp32s3:gpio [2024/02/05 11:34] (current) – jcmvbkbc | ||
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====== GPIO and pin muxing ====== | ====== GPIO and pin muxing ====== | ||
- | Take a look at the [[https:// | + | Take a look at the [[https:// |
+ | {{ : | ||
- | IO MUX pin setting | + | IO MUX pin settings |
< | < | ||
&iomux { | &iomux { | ||
Line 19: | Line 20: | ||
These properties cannot be changed at runtime (short of writing directly to IO_MUX_n_REG registers). | These properties cannot be changed at runtime (short of writing directly to IO_MUX_n_REG registers). | ||
- | When there' | + | When there' |
< | < | ||
& | & | ||
Line 47: | Line 48: | ||
}; | }; | ||
</ | </ | ||
+ | |||
+ | Other properties of a GPIO pin (input/ | ||
+ | < | ||
+ | i2c0 { | ||
+ | # | ||
+ | # | ||
+ | compatible = " | ||
+ | |||
+ | sda-gpios = <& | ||
+ | scl-gpios = <& | ||
+ | |||
+ | pinctrl-0 = <& | ||
+ | pinctrl-names = " | ||
+ | |||
+ | mpu6050@68 { | ||
+ | compatible = " | ||
+ | reg = < | ||
+ | interrupt-parent = <& | ||
+ | interrupts = <8 IRQ_TYPE_EDGE_RISING>; | ||
+ | |||
+ | pinctrl-0 = <& | ||
+ | pinctrl-names = " | ||
+ | }; | ||
+ | }; | ||
+ | </ | ||
+ | |||
+ | GPIO pins may need to be in a specific state after boot, but there may be no device that would drive them. In that case they can be brought to that state by the gpio-hog nodes added under the gpio controller node, see [[https:// | ||
+ |
etc/users/jcmvbkbc/linux-xtensa/esp32s3/gpio.1706884396.txt.gz · Last modified: 2024/02/02 17:33 by jcmvbkbc