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--- etc:users:jcmvbkbc:linux-xtensa:esp32s3:gpio [2024/02/02 17:33] – created jcmvbkbc
+++ etc:users:jcmvbkbc:linux-xtensa:esp32s3:gpio [2024/02/05 11:34] (current) – jcmvbkbc
@@ Line 1: / Line 1: @@
 ====== GPIO and pin muxing ======
-Take a look at the [[https://www.espressif.com/sites/default/files/documentation/esp32-s3_technical_reference_manual_en.pdf#subsection.6.3|esp32s3 TRM chapter 6.3]], [[https://www.espressif.com/sites/default/files/documentation/esp32-s3_technical_reference_manual_en.pdf#table.6.2|table 6.2]] and [[https://www.espressif.com/sites/default/files/documentation/esp32-s3_technical_reference_manual_en.pdf#table.6.3|table 6.3]] to understand relation between the IO MUX and the GPIO matrix.
+Take a look at the [[https://www.espressif.com/sites/default/files/documentation/esp32-s3_technical_reference_manual_en.pdf#subsection.6.3|esp32s3 TRM chapter 6.3]], [[https://www.espressif.com/sites/default/files/documentation/esp32-s3_technical_reference_manual_en.pdf#table.6.2|table 6.2]] and [[https://www.espressif.com/sites/default/files/documentation/esp32-s3_technical_reference_manual_en.pdf#table.6.3|table 6.3]] to understand relation between the peripheral signals, IO MUX and the GPIO matrix. Teaser picture:
+{{ :etc:users:jcmvbkbc:linux-xtensa:esp32s3:esp32s3-gpio-matrix-io-mux.png?nolink |}}
-IO MUX pin setting (selected function, drive strength, pull-up, pull-down, input enable) are controlled by the ''iomux: pinctrl@60009000'' node, like this:
+IO MUX pin settings (selected function, drive strength, pull-up, pull-down, input enable) are controlled by the children of the ''iomux: pinctrl@60009000'' node, like this:
 <code>
 &iomux {
@@ Line 19: / Line 20: @@
 These properties cannot be changed at runtime (short of writing directly to IO_MUX_n_REG registers).
-When there's no direct connection for the function in the IO MUX or the pin with direct connection cannot be used a function may be routed through the GPIO matrix to a different GPIO and connected to a different pin. These settings are controlled by the nodes ''gpio_out_mux: gpio_out_mux@60004554'' and ''gpio_in_mux: gpio_in_mux@60004154''. Numbering schemes are different for output and input muxes. E.g. for the ouput mux a GPIO index is mapped to a peripheral signal (table 6.2):
+When there's no direct connection for the function in the IO MUX (e.g. UART2 signals are not there) or the pin with direct connection cannot be used, a function may be routed through the GPIO matrix to a different GPIO and connected to a different pin. These settings are controlled by the children of the nodes ''gpio_out_mux: gpio_out_mux@60004554'' and ''gpio_in_mux: gpio_in_mux@60004154''. Numbering schemes are different for output and input muxes. E.g. for the ouput mux a GPIO index is mapped to a peripheral signal (table 6.2):
 <code>
 &gpio_out_mux {
@@ Line 47: / Line 48: @@
 };
 </code>
+Other properties of a GPIO pin (input/output, normal/open drain, interrupt type) can be controlled through the GPIO API or through the device tree connection for the pin, like the pins 6, 7 and 8 have here:
+<code>
+i2c0 {
+	#address-cells = <1>;
+	#size-cells = <0>;
+	compatible = "i2c-gpio";
+	sda-gpios = <&gpio0 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+	scl-gpios = <&gpio0 7 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+	pinctrl-0 = <&i2c0_pins>;
+	pinctrl-names = "default";
+	mpu6050@68 {
+		compatible = "invensense,mpu6050";
+		reg = <0x68>;
+		interrupt-parent = <&gpio0>;
+		interrupts = <8 IRQ_TYPE_EDGE_RISING>;
+		pinctrl-0 = <&accelerometer0_pins>;
+		pinctrl-names = "default";
+	};
+};
+</code>
+GPIO pins may need to be in a specific state after boot, but there may be no device that would drive them. In that case they can be brought to that state by the gpio-hog nodes added under the gpio controller node, see [[https://github.com/jcmvbkbc/linux-xtensa/blob/v6.7/Documentation/devicetree/bindings/gpio/gpio.txt#L202|Documentation/devicetree/bindings/gpio/gpio.txt]] for the details.