etc:users:jcmvbkbc:qemu-target-xtensa:pipeline
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Cycle-accurate pipeline
5-stage pipeline:
- I instruction memory read;
- R instruction decode, register access;
- E ALU operation, effective address generation;
- this stage may be delayed if it accesses a register affected by an earlier load instruction that has not yet reached M stage;
- M memory access;
- W register write back;
DSYNC < ESYNC < RSYNC < ISYNC
etc/users/jcmvbkbc/qemu-target-xtensa/pipeline.1312759658.txt.gz · Last modified: 2011/08/08 03:27 by jcmvbkbc