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QEMU support for Xtensa

Description

qemu/target-xtensa is a project aimed at development of a free simulator for Tensilica Xtensa processor family.

Although xtensa instruction set specification is open and there's even linux port for xtensa there were no free simulator available.

The project was initiated to lower cost and to speed up development of one of the Motorola Solutions projects and has been carried out exclusively by the OSLL. Started in March 2011 it took 2 months to provide initial ThreadX support, 2 more months to provide linux support and 2 more months to get accepted into the qemu mainline.

Our goal is to make it usable (and preferable:) in real development/production environment.

Now active

TODO

  • xtensa TCG backend

Implementation status

  • core/basic opcodes implementation;
    • [+] and/or/xor/neg/abs;
    • [+] shifts;
    • [+] add[x*]/sub[x*]/add.n/addi.n;
    • [+] call0, callx0, j, b*;
    • [+] l32*, s32*;
    • [+] accurate SR write semantics;
  • options
    • [+] windowed registers;
      • [+] call*/callx*, retw, rotw, rfwo, rfwu;
      • [+] accurate overflow triggering;
    • [+] loop option;
    • [+] extended L32R option;
    • [+] MAC16;
    • [+] coprocessors;
      • [+] floating point;
      • [+] boolean registers/commands;
    • [+] memory protection;
      • [+] no-MMU mode;
      • [+] region protection (with/without translation);
      • [+] MMU mode;
    • cache options;
      • [+] memory attributes;
      • [+] memory accessibility check;
      • [-] memory access timing;
    • [+] debug option;
    • exceptions;
      • [+] debug (only external);
      • [+] break;
      • [+] window overflow/underflow;
      • [+] user/kernel (invalid insn, privileged insn, alignment, division by 0,…);
      • [+] relocatable vectors;
      • [+] external interrupts;
      • [+] timer interrupts;
        • [+] qemu timer to avoid busy looping in waiti;
    • [-] FLIX;
    • [+] wide branches;
  • gdbserver;
    • [+] read/write register, xml register map (not used by gdb);
    • [+] correct SR mapping;
    • [+] debug exception, single step mode;
    • [+] hw/sw breakpoints;
    • [+] gdbserver for different processor types;
  • sample evaluation board;
    • [+] sim platform;
    • xt2000 platform;
      • [+] UART (reuse existing 16550 serial);
      • [+] xtsonic (reuse existing dp8393x NIC);
      • [-] LED;
    • [+] lx200/60/110 platform;
      • [+] UART (reuse existing 16550 serial);
      • [+] opencores ethernet;
    • [+] linux-user
  • simulation quality;
    • [+] pass command line arguments to argc/argv SIMCALLs;
    • [+] TB chaining;
  • [+] external configuration (overlay reuse);
  • [+] automatic regression test suite;
  • [+] SMP support (interrupt distributor, WER/RER);
  • [-] cycle accurate pipeline;

Events

I guess you can just make sure you don't mark new registers as PRIVILEGED in
   ./gdb/xtensa-config.c
etc/users/jcmvbkbc/qemu-target-xtensa.1548826207.txt.gz · Last modified: 2019/01/30 08:30 by jcmvbkbc